The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the semiconductor integrated circuit device, and more particularly to a design for testability capable of reducing an over-head caused by having a test circuit in the semiconductor integrated circuit device, for example, an effective technique to be applicable to a semiconductor integrated circuit such as a system LSI (Large Scale Integrated Circuit) having a RAM (Random Access Memory) provided therein.
In general, as a general design for testability in a logic LSI referred to as a system LSI having a RAM, a CPU and the like mounted thereon, there has been often used a scanning path methodology in which a flip-flop constituting an internal logic circuit is serially connected to input test data and the internal logic circuit is operated to check a logic status. Ten years or more have passed since this technology has been proposed as an LSSD (Level Sensitive Scan Design) method, and furthermore, this technology has an over-head of approximately 35% for hardware and a fault coverage of approximately 85%. There has been a problem in that a great deal of endeavor is required to increase the coverage still more.
In order to increase the fault coverage, moreover, it is necessary to remarkably increase the pattern capacity of a test pattern generator provided in a tester. Consequently, the price of the tester is increased considerably. Furthermore, test data should be input as serial data. Therefore, a great deal of time is required to input a test pattern. Therefore 50% or more of a test time is required for inputting the test pattern so that the effective availability of the tester is also reduced.
In addition to the scanning path methodology, there has been a BIST (Built-In Self Test) methodology in which a random pattern generator and a signature compression circuit are mounted on a chip as test circuits. The BIST methodology uses a random test pattern differently from logic testability based on a test pattern generated in accordance with a fault coverage algorithm to be used for the scanning path methodology. For this reason, whether or not a proper fault coverage is maintained is a big problem, and various techniques are to be developed to obtain an appropriate methodology.
Also in the case in which the BIST methodology is employed, furthermore, it is necessary to carry out a connection to a high-speed tester having high function used in the scanning path methodology, thereby performing measurement according to the control of the tester. In a test to be carried out in the BIST circuit, an expensive tester is often caused to stand by as a simple waiting time processing. Therefore, a test cost is not reduced. In order to eliminate such a drawback, the present inventors previously proposed a technique referred to as a so-called xe2x80x9clogic with test functionxe2x80x9d in which a logic tester is constructed in a chip to carry out a self test, wherein a test circuit other than the BIST is provided in a chip to carry out measurement. In this methodology, an expensive tester is not required. Therefore, the test cost can be reduced considerably. In the same manner as in the BIST methodology, however, there has been a problem in that the over-head of hardware is great and the yield of a product is reduced due to faults of a test circuit itself which is mounted on a chip.
In order to solve such a problem, the present inventors had proposed a technique referred to as a so-called xe2x80x9cnon over-head test techniquexe2x80x9d in which an FPGA (Field Programmable Gate Array) is provided on a chip and an ALPG (Algorithmic Pattern Generator) is constructed by the FPGA to generate a test pattern in accordance with a predetermined algorithm to carry out a test and to reconstruct an ordinary logic circuit on the FPGA after the test ends (International Publication WO00/62339). According to this technique, a circuit referred to as a so-called self-testability type FPGA capable of detecting a self fault is provided in a user logic circuit and a test circuit is constituted to carry out a self test and to finally mount a user circuit on the FPGA, thereby reducing the over-head of hardware with test circuit mounting. In this technique, the FPGA is set to be the self-testability type circuit. Therefore, fault exposure is detected by itself and information about a fault portion is output to the outside, and a circuit can be constituted except for the fault portion when constructing a logic tester on the FPGA through a test HDL (Hardware Description Language) or constituting a user circuit. Therefore, there has been a character that a reduction in yield can be avoided.
Then, the present inventors have further investigated the technique referred to as the so-called xe2x80x9cnon over-head test techniquexe2x80x9d described above. As a result, it has been apparent that there are the following drawbacks. For example, in this technique, it is necessary to introduce a novel device process referred to as the FPGA. Although semiconductor manufactures providing the FPGA or a product mounting the FPGA to the market can implement this technique by slightly changing a process, general semiconductor manufactures do not manufacture the FPGA or the product mounting the FPGA. In order to develop this technique, therefore, it is necessary to design the FPGA and to improve a novel process for forming the FPGA on a semiconductor chip.
Moreover, the present inventors have proposed a technique referred to as a so-called xe2x80x9cself-configuration chipxe2x80x9d for memory device redundancy separately from the above-mentioned design for testability. In this technique, a memory is utilized as a re-configuration logic circuit by writing truth data of a combination circuit to the memory, inputting an address and outputting a predetermined logic result. The output of the memory is fed back to the input so that a sequential circuit as well as the combination circuit can be constituted. Therefore, the present inventors found that a so-called xe2x80x9cself-configuration chipxe2x80x9d capable of constituting an optional logic can be implemented and therefore filed the application. The present inventors further invented that application of the xe2x80x9cself-configuration chipxe2x80x9d technique to the xe2x80x9cnon over-head test techniquexe2x80x9d do not require the FPGA and the problem of the design of the FPGA and the development of the process can be solved.
It is, therefore, an object of the present invention to provide, without introducing a novel device process referred to as the FPGA, a semiconductor integrated circuit device and a method of manufacturing the semiconductor integrated circuit device in which a test circuit is provided in a chip to test a logic circuit in the chip so as to be capable of performing a logic test having less overhead.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
The summary of the typical invention disclosed in this application will be described below.
More specifically, the present invention provides a semiconductor integrated circuit device comprising a storage circuit capable of reading and writing data in response to an input of an address signal, and a feedback path for feeding back a signal corresponding to data read from the storage circuit to an input terminal side of the address signal, wherein an input signal of a logic circuit is input as the address signal to the storage circuit and data are written to the storage circuit such that the data read from the storage circuit are changed into a logical output signal expected to the input signal so that the storage circuit can be operated as a logic circuit having desirable logic function.
According to the above-mentioned means, the storage circuit provided in the semiconductor integrated circuit device can be utilized as the logic circuit. Therefore, the test circuit for checking the other circuit in a semiconductor chip can be constituted on the storage circuit. Consequently, the logic test circuit can be constituted in the chip without introducing a novel device process of FPGA, and the storage circuit constituting the test circuit can be used as an ordinary storage circuit after the test is completed. Thus, it is possible to implement the test circuit having less over-head of hardware.
Moreover, it is desirable that the semiconductor integrated circuit device should further comprise a switch matrix capable of switching an input address signal sent to an input terminal and a signal read from the storage circuit and fed back through the feedback path and for supplying the switched signal to the storage circuit; and storage means for storing control information of each switch in the switch matrix. Consequently, a sequential circuit having an output varied depending on a last state as well as a combination circuit having optional logic function can be constituted in the storage circuit, and more complicated logic function can be implemented by using the storage circuit. In addition, the switch matrix and the storage means for storing control information of each switch in the switch matrix are provided. Therefore, it is very easy to constitute an optional sequential circuit in the storage circuit or an ordinary storage circuit by rewriting the control information to be stored in the storage means.
The present invention provides another semiconductor integrated circuit device comprising a plurality of storage circuits capable of reading and writing data in response to an input of an address signal; a part of the storage circuits including a memory array capable of reading and writing data from a memory cell specified by the address signal, an address decoder for decoding the address signal and generating a signal to select the memory cell; comparing means for comparing data written to the memory array with data read from the memory array; and variable address converting means for converting the address signal supplied to the address decoder based on a result of the comparison of the comparing means, wherein data are written to the storage circuit such that the data read from the storage circuit are changed into a logical output signal expected to the input signal so that the storage circuit can be operated as a logic circuit having desirable logic function.
According to the above-mentioned means, the address converting circuit is provided. Therefore, the write data can be written to the storage circuit to avoid a fail portion in the storage circuit and to obtain a desirable logical output signal. Consequently, yield can be enhanced.
Moreover, it is desirable that the semiconductor integrated circuit device should further comprise data holding means capable of holding data read from the memory array; a feedback path for feeding back the data held in the data holding means to an input side of the address decoder; a switch matrix capable of switching an input address signal or an output signal of the data holding means supplied through the feedback path so as to supply the switched signal to the variable address converting means; and storage means for storing control information of each switch in the switch matrix. Consequently, a sequential circuit having an output varied depending on a last state as well as a combination circuit having optional logic function can be constituted in the storage circuit, and more complicated logic function can be implemented by using the storage circuit.
Furthermore, the variable address converting means is constituted by a memory array including a plurality of memory cells; an address decoder for selecting a memory cell in the memory array based on an input address signal; reading means for amplifying a signal read from the memory array; and means for updating the input address signal based on a control signal. Consequently, it is possible to implement the variable address converting circuit by using the storage circuit without designing a novel circuit. Thus, a designer""s burden can be relieved.
The present invention provides a further semiconductor integrated circuit device comprising a plurality of storage circuits; a first signal line group for supplying an address signal to the storage circuits; and a second signal line group for transmitting a write data signal and a read data signal of the storage circuits;
the storage circuits including a memory array capable of reading and writing data from a memory cell specified by the address signal; an address decoder for decoding the address signal and generating a signal to select a memory cell in the memory array; a feedback path for feeding back data read from the memory array to an input side of the address decoder; a switch matrix capable of switching an input address signal or a signal fed back through the feedback path so as to supply the switched signal to the address decoder, and storage means for storing control information of each switch in the switch matrix,
wherein the switch matrix and the storage means for storing control information of each switch in the switch matrix are provided to be capable of optionally connecting a signal line of the first signal line group and a signal line of the second signal line group.
According to the above-mentioned means, the storage circuits provided in the semiconductor integrated circuit device can be utilized as the logic circuit. Therefore, the test circuit for checking the other circuit in a semiconductor chip can be constituted by using the storage circuits. Consequently, the logic test circuit can be constituted in the chip without introducing a novel device process of FPGA, and the storage circuit constituting the test circuit can be used as an ordinary storage circuit after the test is completed. Thus, it is possible to implement the test circuit having less over-head of hardware.
It is desirable that the semiconductor integrated circuit device should further comprise a test access port to be an interface circuit for a test; the storage circuit constituting the test circuit capable of inputting and outputting a signal to and from an external device through the test access port. Consequently, the number of terminals for the test with the application of the present invention is slightly increased, and the number of pins in the whole semiconductor integrated circuit device can be decreased.
The storage circuit may be a writable nonvolatile memory or volatile memory, and desirably, the volatile memory. The nonvolatile memory requires a large number of peripheral circuits for writing such as a booster circuit and a time required for the writing is longer than that in the volatile memory. However, the use of the volatile memory can prevent an occupied area from being increased and a writing time from being prolonged.
Furthermore, the present invention provides a method of manufacturing a semiconductor integrated circuit device comprising a logic circuit and a plurality of storage circuits; a part of the storage circuits including a memory array capable of reading and writing data from a memory cell specified by the address signal; an address decoder for decoding the address signal and generating a signal to select a memory cell in the memory array; a feedback path for feeding back data read from the memory array to an input side of the address decoder; a switch matrix capable of switching an input address signal or a signal fed back through the feedback path so as to supply the switched signal to the address decoder; and storage means for storing control information of each switch in the switch matrix; and the part of the storage circuit acting as a storage circuit capable of constituting an optional logic based on data written to the memory array, comprising the steps of constituting, on the storage circuit capable of configuring an optional logic, a test circuit for checking another storage circuit or a logic circuit; testing the other storage circuit and the logic circuit by the test circuit, and reconstituting the storage circuit to be operated as an ordinary storage circuit after the test for another circuit and the logic circuit is completed.
According to the above-mentioned means, it is possible to carry out a self test through the test circuit constituting the storage circuit in the chip even if a test device having high function is not used. Therefore, it is possible to test a large number of semiconductor integrated circuit devices at the same time. Consequently, a manufacturing cost can be reduced considerably and a time required for the test can also be shortened.
Moreover, it is desirable that the method of manufacturing a semiconductor integrated circuit device should further comprise a redundancy processing step of replacing a fail memory cell detected at the test step with a spare memory cell after completing the test of the storage circuit in a case in which another storage circuit includes a redundant circuit for replacing the fail memory cell with the spare memory cell. Consequently, the redundancy of the fail memory cell as well as the test of other storage circuits can also be carried out by using the test circuit constituted in the storage circuit on the chip. Therefore, the burden of the external test device can also be relieved and the cost of the test can be reduced considerably.
Furthermore, it is desirable that at the testing step to be carried out by the test circuit, a result of the test obtained by the test circuit should be stored in a storage circuit other than the storage circuit constituting the test circuit. Consequently, the external device does not always monitor a signal indicative of the result of the test output from the external terminal of the semiconductor integrated circuit device during the test carried out by the test circuit, and the results of the test can be collectively read from the internal storage circuit after the test is completed. Thus, the efficiency of the test can be enhanced considerably.
Furthermore, at the step of constituting a test circuit on the storage circuit capable of configuring an optional logic, design data having a function level described in a hardware description language are decoded by control means and a signal for determining a logical structure of the storage circuit is given from the control means to the storage circuit so that a logic circuit having desirable logic function is constituted.
Consequently, the test circuit can be constituted in an SRAM to be a storage circuit of a self-configuration type based on the HDL description. Therefore, the test circuit can easily be constructed in the chip by using a computer. In addition, a test program to be used in an ordinary tester is available and debug for the test circuit is not required. Therefore, it is possible to implement the semiconductor integrated circuit device capable of considerably reducing the man-hour of a test design.